Research Projects

• MOST, Taiwan: Fellowship to pursue advnaced research in Japan, “High-Performance Memory System Design for MPSoCs with 3D-stacked Phase Change Memory based FPGAs”, PI, 08/01/2019~07/31/2020, NT$ 739,600.
• MOST, Taiwan: “Energy-Efficient Memory System Design for the Hybrid Architecture of CPUs with FPGAs for Mobile Devices”, PI, 08/01/2018 ~ 07/31/2020.
  Year 1: NT$ 801,000.
  Year 2: NT$ 726,000.
• MOST, Taiwan: “Design of Memory System for Multi-Processor System-on-Chips with 3D-stacked Emerging Non-Volatile Memories”, PI, 08/01/2017 ~ 07/31/2018, NT$ 578,000.
• MOST, Taiwan: “Resource Synthesis Framework for Multi-Processor System-on-Chips with 3D-stacked Hybrid Memory”, PI, 08/01/2016 ~ 07/31/2017, NT$ 612,000.
• MOST, Taiwan: “Thermal-aware Hardware/Software Co-Design for Multi-Processor System-on-Chip with 3D-stacked Memories”, PI, 08/01/2014 ~ 07/31/2015, NT$ 612,000.
• MOST, Taiwan: “Resource Allocation for Multi-Processors Systen-on-Chips with Single-ISA Heterogeneous Multi-core Architecture”, PI, 08/01/2013 ~ 07/31/2014, NT$ 600,000.
• MOST, Taiwan: “Synthesis of Resource and Data Allocation for MPSoCs with 3D-Stacked SRAMs”, PI, 08/01/2012 ~ 07/31/2013, NT$ 554,000.
• MOST, Taiwan: “Thermal and Performance-aware System Synthesis for 3D …” 

Research Achievements

Journal Papers

1. Yi-Jung Chen*, Wen-Wei Chang, Chia-Yin Liu, Cheng-En Wu, Bo-Yuan Chen, Ming-Ying Tsai, “Processors Allocation for MPSoCs with Single ISA Heterogeneous Multi-core Architecture”, in IEEE Access, Vol. 5, 4028-4036, 2017. (First/corresponding author)
2. Yi-Jung Chen*, Chia-Ling Yang, Ping-Sheng Lin, and Yi-Chiang Lu, “Opportunities of Synergistically Adjusting Voltage-Frequency Levels of Cores and DRAMs in CMPs with 3DStacked DRAMs for Efficient Thermal Control”, ACM Applied Computing Review, 16, No. 1, pp. 26-35, Mar. 2016. (First/corresponding author)
3. Che-Wei Chang, Geng-You Chen, Yi-Jung Chen, Chia-Wei Yeh, Pei Yin Eng, Ana Cheung, Chia-Lin Yang: Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level IEEE Transactions on Computers 66(8): 1457-1463, Jan. 2017.
4. Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen*, Chia-Lin Yang, Cheng-Yuan Michael Wang, “SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs”, ACM Transactions on Architecture and Code Optimization (TACO), Vol. 12, No. 2. 19:19:1-19:19:24, Apr. 2015. (Corresponding author)
5. Yi-Jung Chen, Chia-Lin Yang and Yen-Sheng Chang, “An architectural co-synthesis algorithm for energy-aware Network-on-Chip design”. Journal of Systems Architecture – Embedded Systems Design, Vol. 55, 5-6, pp. 299-309, 2009.
6. Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang Sam Han, “Improved Modulo (2n+1) Multiplier for IDEA”. Journal of Information Science Engineering, Vol. 23, No. 3, pp. 911-923, 2007.

Conference Papers

1. Chia-Yin Liu, Cheng-En Wu, Yi-Jung Chen*, “Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories”, in proceedings of 2018 ACM Research in Adaptive and Convergent Systems (RACS), 243-248, Oct. 2018. (Corresponding author)
2. Yi-Jung Chen*, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu, “Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs”, in Proceedings of 2015 ACM Research in Adaptive and Convergent Systems (RACS), pp. 430-436, Oct. (First/corresponding author)
3. Yi-Jung Chen*, Chia-Lin Yang, Jian-Jia Chen, “Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs”, in Proceedings of 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 458-465, Nov. 2012. (First/corresponding author)
4. Yi-Jung Chen*, Chia-Lin Yang, Po-Han Wang, “PM-COSYN: PE and memory co-synthesis for MPSoCs”. In Proceedings of 2010 Design Automation and Test in Europe (DATE), pp. 1590-1595, Mar. 2010. (First/corresponding author)
5. Meng-Ling Tsai, Yi-Jung Chen*, Yi-Ting Chen, Ru-Hua Chang, “Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs”, in Proceedings of 2014 IEEE/ACM Design Automation and Test in Europe (DATE), pp 1-6, Mar. 2014. (Corresponding author)
6. Ping-Sheng Lin, Yi-Jung Chen*, Chia-Lin Yang, Yi-Chang Lu, “Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs”, in Proceedings of 2013 IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED), pp. 304, Sep. (Corresponding author)
7. Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen*, Chia-Lin Yang, Cheng-Yuan Michael Wang, “SECRET: Selective error correction for refresh energy reduction in DRAMs”, in Proceedings of 2012 IEEE International Conference on Computer Design (ICCD), pp. 67-74, 2012.

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